The introduction of large scale integration techniques has brought about the construction of large memory arrays on a single silicon chip. These memory arrays are made up of a large number of storage cells fabricated with a high packing density with the lowest possible power consumption.
There is a continuing demand to increase the storage cell density for semiconductor memory chips. The greater density reduces the manufacturing cost per unit of memory storage. However, the limits of fabrication density are rapidly being reached for existing manufacturing equipment.
With the advance of semiconductor technology the technique of ion implantation has become well developed. This technique permits an accurate fabrication of the threshold voltage for a transistor such that the transistor can be caused to switch at an accurately determined amplitude of drive signal. This technique of ion implantation has been implemented for a multi-bit read only memory circuit which is described in U.S. Pat. No. 4,202,044 issued to Beilstein, Jr., et al., on May 6, 1980 and entitled, "Quanternary FET Read Only Memory."
In view of the demand for greater storage density in semiconductor memories and the ability to precisely fabricate threashold voltages in field effect transistors, there exists a need for a read only memory circuit which can utilize multi-level ion implementation to provide a plurality of bits of storage in each memory storage transistor. Such a read only memory circuit further requires a fast and accurate sensing circuit for reading the multi-bit data stored in the multi-bit memory cells.